Intel is not a US “national champion,” but there is a lot riding on its high-risk, high-payoff struggle to reemerge as the world’s leading semiconductor chip manufacturer after falling behind its two chief competitors, Samsung and Taiwan Semiconductor Manufacturing Corporation (TSMC), a few years ago. Intel CEO Pat Gelsinger has proven himself an adroit political tactician, successfully wooing political leaders from US President Joe Biden to French President Emmanuel Macron. And he, along with other US tech leaders, provided strong impetus for the passage of the CHIPS and Science Act, which provides large subsidies for new semiconductor plants built in the US. It remains to be seen whether Gelsinger’s technological and financial prowess match his political savviness.
This piece will discuss key challenges and trade-offs, starting on the technological frontier. Part II will address more broadly the fraught geopolitical and economic arena.
Regarding technology competition, Gelsinger made the crucial decision last year to enter the foundry business despite Intel’s earlier manufacturing missteps. Today, both Samsung and TSMC are about to start mass producing 3-nanometer (nm) chips—and, in the future, 2 nm—while Intel remains behind in the 7 nm phases after taking years to work out bugs in its 10 nm chips.
Gelsinger has forcefully attempted to close this technology gap; he has committed to a huge capital investment (which I will address in Part II of this piece) and has siphoned away key technical talent from his rivals. Recently, Gelsinger boasted a new semiconductor chip based on the so-called “gate all around” disaggregated chip design that combines several components (“chiplets”) into one semiconductor. Such a chip design would allow Intel to buy and incorporate advanced chips it does not currently produce (say, from TSMC) and incorporate them into a final product, utilizing the company’s advanced packaging techniques. It should be noted that other semiconductor companies are also moving in this direction, and a number have agreed to work on common interoperability standards for chiplets.
Two points, finally: First, both Samsung and TSMC are also pushing ahead with disaggregated chip designs, and Samsung has promised to mass produce its upcoming 3nm chip. All of this is to say that while Intel is playing catch-up, both its rivals are also pouring tens of billions of dollars into programs to advance their own technical prowess. TSMC has announced a $100 billion expansion plan over the next few years, and Samsung has pledged $360 billion over the next five years to advance in microelectronics and biotechnology.
Second, Intel must overcome internal production issues and resulting customer wariness that it will deliver on time with sustainable quality. While Intel has immense experience collaborating with other companies on design, it must now bring along customers for chips commissioned for manufacturing. As outside experts have noted, potential customers will evaluate the upcoming 20A and 18A chips (Intel terminology) in 2024 and 2025. Still, Gelsinger and his team are acutely aware of these challenges and have moved to have engineers and technical talent carefully shepherd customers through the future manufacturing process.
As one expert noted: “For Intel, working with an external customer is novel, so there could be more bumps along the way . . . but anyone worth their salt would anticipate and plan for that.” That, no doubt, is what Gelsinger is counting on.
The post Intel’s High-Wire Act, Part I appeared first on American Enterprise Institute – AEI.